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9.5 RON 15 V/+12 V/5 V iCMOS Serially-Controlled Octal SPST Switches ADG1414
FEATURES
SPI interface Supports daisy-chain mode 9.5 on resistance @ 25C 1.6 on-resistance flatness Fully specified at 15 V, +12 V, 5 V 3 V logic-compatible inputs Rail-to-rail operation 24-lead TSSOP and 24-lead 4 mm x 4 mm LFCSP
FUNCTIONAL BLOCK DIAGRAM
ADG1414
S1 S2 S3 S4 S5 S6 S7 S8 INPUT SHIFT REGISTER D1 D2 D3 D4 D5 D6 D7 D8
APPLICATIONS
Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communication systems
SDO
08497-001
SCLK DIN SYNC
RESET/VL
Figure 1.
GENERAL DESCRIPTION
The ADG1414 is a monolithic complementary metal-oxide semiconductor (CMOS) device containing eight independently selectable switches designed on an industrial CMOS (iCMOS(R)) process. iCMOS is a modular manufacturing process combining high voltage CMOS and bipolar technologies. iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduce the package size. The ADG1414 is a set of octal SPST (single-pole, single-throw) switches controlled via a 3-wire serial interface. On resistance is closely matched between switches and is very flat over the full signal range. Each switch conducts equally well in both directions and the input signal range extends to the supplies.
Data is written to these devices in the form of eight bits; each bit corresponds to one channel. The ADG1414 utilizes a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with standard SPI, QSPITM, MICROWIRETM, and DSP interface standards. The output of the shift register, SDO, enables a number of these parts to be daisy chained. On power-up, all switches are in the off condition, and the internal registers contain all zeros.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 50 MHz serial interface. 9.5 on resistance. 1.6 on-resistance flatness. 24-lead TSSOP and 4 mm x 4 mm LFCSP packages.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
ADG1414 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 15 V Dual Supply ....................................................................... 3 12 V Single Supply ........................................................................ 4 5 V Dual Supply ......................................................................... 6 Continuous Current per Channel .............................................. 7 Timing Characteristics ................................................................ 8 Absolute Maximum Ratings.......................................................... 10 Thermal Resistance .................................................................... 10 ESD Caution................................................................................ 10 Pin Configurations and Function Descriptions ..........................11 Typical Performance Characteristics ........................................... 13 Test Circuits ..................................................................................... 16 Terminology .................................................................................... 18 Theory of Operation ...................................................................... 19 Serial Interface ............................................................................ 19 Input Shift Register .................................................................... 19 Power-On Reset .......................................................................... 19 Daisy Chaining ........................................................................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
10/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG1414 SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V 10%, VSS = -15 V 10%, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) +25C -40C to +85C -40C to +125C VSS to VDD 9.5 11.5 0.55 1 1.6 1.9 0.05 0.15 0.05 0.15 0.1 0.3 1 1 2 2 2 4 2.0 0.8 0.001 0.1 Digital Input Capacitance, CIN LOGIC OUTPUTS (SDO) Output Low Voltage, VOL 1 High Impedance Leakage Current High Impedance Output Capacitance1 DYNAMIC CHARACTERISTICS1 tON tOFF Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion (THD + N) -3 dB Bandwidth Insertion Loss CD, CS (Off ) CD, CS (On) 4 0.4 0.6 0.001 1 4 14 16 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ V max V max A typ A max pF typ Test Conditions/Comments
VDD = +13.5 V, VSS = -13.5 V, VS = 10 V, IS = -10 mA; see Figure 23 VDD = +13.5 V, VSS = -13.5 V, VS = 10 V, IS = -10 mA VDD = +13.5 V, VSS = -13.5 V, VS = 10 V, IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = 10 V; see Figure 24 VS = 10 V, VD = 10 V; see Figure 24 VS = VD = 10 V; see Figure 25
On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current
1.5 2.15
1.7 2.3
VIN = VGND or VL
ISINK = 3 mA ISINK = 6 mA
75 93 25 35 10 -73 -75 0.05 256 0.55 8 32
110 35
120 35
ns typ ns max ns typ ns max pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ
RL = 100 , CL = 35 pF VS = 10 V; see Figure 30 RL = 100 , CL = 35 pF VS = 10 V; see Figure 30 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 RL = 110 , 15 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 f = 1 MHz f = 1 MHz
Rev. 0 | Page 3 of 20
ADG1414
Parameter POWER REQUIREMENTS IDD IL Inactive IL Active @ 30 MHz IL Active @ 50 MHz ISS VDD/VSS
1
+25C 0.001
-40C to +85C
-40C to +125C
Unit A typ A max A typ A max mA typ mA max mA typ mA max A typ A max V min/max
Test Conditions/Comments VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VL Digital inputs = 0 V or VL Digital inputs toggle between 0 V and VL Digital inputs toggle between 0 V and VL Digital inputs = 0 V or VL
1 0.3 1 0.26 0.3 0.42 0.5 0.001 1 4.5/16.5 0.55 0.35
Guaranteed by design, not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) +25C -40C to +85C -40C to +125C 0 to VDD 18 21.5 0.55 1.2 5 6 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) 0.02 0.15 0.02 0.15 0.05 0.3 1 2 26 28.5 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ VDD = 10.8 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = VD = 1 V or 10 V; see Figure 25 Test Conditions/Comments
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = -10 mA; see Figure 23 VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = -10 mA VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = -10 mA
On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON))
1.6
1.8
6.9
7.3
Drain Off Leakage, ID (Off )
1 2
2 4 2.0 0.8
Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current Digital Input Capacitance, CIN
0.001 0.1 4
VIN = VGND or VL
Rev. 0 | Page 4 of 20
ADG1414
Parameter LOGIC OUTPUTS (SDO) VOL, Output Low Voltage 1 High Impedance Leakage Current High Impedance Output Capacitance1 DYNAMIC CHARACTERISTICS1 tON tOFF Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth Insertion Loss CD, CS (Off ) CD, CS (On) POWER REQUIREMENTS IDD IL Inactive IL Active @ 30 MHz +25C -40C to +85C -40C to +125C 0.4 0.6 1 4 Unit V max V max A max pF typ Test Conditions/Comments ISINK = 3 mA ISINK = 6 mA
145 185 35 45 8 -70 -75 240 1.15 12 33 0.001
220 46
240 46
ns typ ns max ns typ ns max pC typ dB typ dB typ MHz typ dB typ pF typ pF typ A typ A max A typ A max mA typ mA max mA typ mA max A typ A max V min/max
RL = 100 , CL = 35 pF VS = 8 V; see Figure 30 RL = 100 , CL = 35 pF VS = 8 V; see Figure 30 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 RL = 50 , CL = 5 pF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 f = 1 MHz f = 1 MHz VDD = +13.2 V Digital inputs = 0 V or VL Digital inputs = 0 V or VL Digital inputs toggle between 0 V and VL Digital inputs toggle between 0V and VL Digital inputs = 0 V or VL
1 0.3 1 0.26 0.3 IL Active @ 50 MHz 0.42 0.5 ISS VDD/VSS
1
0.35
0.55 1 4.5/16.5
0.001
Guaranteed by design, not subject to production test.
Rev. 0 | Page 5 of 20
ADG1414
5 V DUAL SUPPLY
VDD = +5 V 10%, VSS = -5 V 10%, VL = 2.7 V to VDD, GND = 0 V, unless otherwise noted. Table 3.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) +25C -40C to +85C -40C to +125C VSS to VDD 21 25 0.6 1.3 5.2 6.4 0.02 0.15 0.02 0.15 0.05 0.3 1 1 2 2 2 4 2.0 0.8 0.001 0.1 Digital Input Capacitance, CIN LOGIC OUTPUTS (SDO) VOL, Output Low Voltage 1 High Impedance Leakage Current High Impedance Output Capacitance1 DYNAMIC CHARACTERISTICS1 tON tOFF Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion, THD + N -3 dB Bandwidth Insertion Loss CD, CS (Off ) CD, CS (On) 4 0.4 0.6 1 4 29 32 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ V max V max A max pF typ Test Conditions/Comments
VDD = +4.5 V, VSS = -4.5 V, VS = 4.5 V, IS = -10 mA; see Figure 23 VDD = +4.5 V, VSS = -4.5 V, VS = 4.5V, IS = -10 mA VDD = +4.5 V, VSS = -4.5 V, VS = 4.5 V; IS = -10 mA VDD = +5.5 V, VSS = -5.5 V VS = 4.5 V, VD = 4.5 V; see Figure 24 VS = 4.5 V, VD = 4.5 V; see Figure 24 VS = VD = 4.5 V; see Figure 25
On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current
1.7 7.3
1.9 7.6
VIN = VGND or VL
ISINK = 3 mA ISINK = 6 mA
190 250 45 60 7 -70 -75 0.14 256 1 11 35
290 65
320 70
ns typ ns max ns typ ns max pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ
RL = 100 , CL = 35 pF VS = 3 V; see Figure 30 RL = 100 , CL = 35 pF VS = 3 V; see Figure 30 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 RL = 110 , 5 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 f = 1 MHz f = 1 MHz
Rev. 0 | Page 6 of 20
ADG1414
Parameter POWER REQUIREMENTS IDD IL Inactive IL Active @ 30 MHz IL Active @ 50 MHz ISS VDD/VSS
1
+25C 0.001
-40C to +85C
-40C to +125C
Unit A typ A max A typ A max mA typ mA max mA typ mA max A typ A max V min/max
Test Conditions/Comments VDD = +5.5 V, VSS = -5.5 V Digital inputs = 0 V or VL Digital inputs = 0 V or VL Digital inputs toggle between 0 V and VL Digital inputs toggle between 0 V and VL Digital inputs = 0 V or VL
1 0.3 1 0.26 0.3 0.42 0.5 0.001 1 4.5/16.5 0.55 0.35
Guaranteed by design, not subject to production test.
CONTINUOUS CURRENT PER CHANNEL
Table 4. Eight Channels On
Parameter CONTINUOUS CURRENT PER CHANNEL 1 15 V Dual Supply 24-Lead TSSOP (JA = 112.6C/W) 24-Lead LFCSP (JA = 30.4C/W) 12 V Single Supply 24-Lead TSSOP (JA = 112.6C/W) 24-Lead LFCSP (JA = 30.4C/W) 5 V Dual Supply 24-Lead TSSOP (JA = 112.6C/W) 24-Lead LFCSP (JA = 30.4C/W)
1
25C
85C
125C
Unit
Test Conditions/Comments VDD = +13.5 V, VSS = -13.5 V
67 121 64 115 48 86
46 75 44 72 35 57
31 42 30 41 22 36
mA max mA max VDD = 10.8 V, VSS = 0 V mA max mA max VDD = +4.5 V, VSS = -4.5 V mA max mA max
Guaranteed by design, not subject to production test.
Table 5. One Channel On
Parameter CONTINUOUS CURRENT PER CHANNEL 1 15 V Dual Supply 24-Lead TSSOP (JA = 112.6C/W) 24-Lead LFCSP (JA = 30.4C/W) 12 V Single Supply 24-Lead TSSOP (JA = 112.6C/W) 24-Lead LFCSP (JA = 30.4C/W) 5 V Dual Supply 24-Lead TSSOP (JA = 112.6C/W) 24-Lead LFCSP (JA = 30.4C/W)
1
25C
85C
125C
Unit
Test Conditions/Comments VDD = +13.5 V, VSS = -13.5 V
169 295 161 281 122 214
97 139 93 135 76 114
48 55 47 54 43 51
mA max mA max VDD = 10.8 V, VSS = 0 V mA max mA max VDD = +4.5 V, VSS = -4.5 V mA max mA max
Guaranteed by design, not subject to production test.
Rev. 0 | Page 7 of 20
ADG1414
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2). VDD = 4.5 V to 16.5 V; VSS = -16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 6.
Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 3 t12
1 2
Limit at TMIN, TMAX 20 9 9 5 5 5 5 15 5 5 40 15
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min
Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK active edge setup time Data setup time Data hold time SCLK active edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK active edge ignored SCLK active edge to SYNC falling edge ignored SCLK rising edge to SDO valid Minimum RESET pulse width
Guaranteed by design and characterization, not production tested. Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = -16.5 V to 0 V, VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V. 3 Measured with the 1 k pull-up resistor to VL and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode.
Timing Diagrams
t10
SCLK
t1
t9
t8 t4
SYNC
t3
t2
t7
t6 t5
DIN DB7
DB0
t12
Figure 2. Serial Write Operation
Rev. 0 | Page 8 of 20
08497-002
RESET
ADG1414
t1
SCLK 8 16
t8
SYNC
t4
t3
t2 t7
t9
t5 t6
DIN DB7 DB0 DB7 DB0
INPUT WORD FOR DEVICE N
INPUT WORD FOR DEVICE N + 1
t11
SDO DB31 DB0
08497-003
UNDEFINED
INPUT WORD FOR DEVICE N
Figure 3. Daisy-Chain Timing Diagram
Rev. 0 | Page 9 of 20
ADG1414 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 7.
Parameter VDD to VSS VDD to GND VSS to GND VL to GND Analog Inputs1 Digital Inputs1 Continuous Current, Sx or Dx Pins Peak Current, Sx or Dx (Pulsed at 1 ms, 10% Duty Cycle Max) TSSOP Package LFCSP Package Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb free Time at Peak Temperature
1
Rating 35 V -0.3 V to +25 V +0.3 V to -25 V -0.3 V to +7 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND - 0.3 V to VL + 0.3 V or 30 mA, whichever occurs first Table 4 specifications + 15%
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
THERMAL RESISTANCE
Table 8. Thermal Resistance
Package Type 24-Lead TSSOP1 24-Lead LFCSP2 JA 112.6 30.4 JC 50 Unit C/W C/W
300 mA 400 mA -40C to +125C -65C to +150C 150C 260C 10 sec to 40 sec
1 2
4-layer board. 4-layer board and exposed paddle soldered to VSS.
ESD CAUTION
Overvoltages at the analog and digital inputs are clamped by internal diodes. Limit the current to the maximum ratings given.
Rev. 0 | Page 10 of 20
ADG1414 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SCLK 1 VDD 2 DIN 3 GND 4 S1 5 D1 6 S2 7 D2 8 S3 9 D3 10 S4 11 D4 12
24 SYNC 23 RESET/VL 22 SDO 21 VSS
ADG1414
TOP VIEW (Not to Scale)
20 S8 19 D8 18 S7 17 D7 16 S6 15 D6
08497-004
GND S1 D1 S2 D2 S3
1 2 3 4 5 6
24 23 22 21 20 19
PIN 1 INDICATOR
DIN VDD SCLK SYNC RESET/VL SDO
ADG1414
TOP VIEW (Not to Scale)
18 17 16 15 14 13
VSS S8 D8 S7 D7 S6
D3 S4 D4 D5 S5 D6
14 S5 13 D5
7 8 9 10 11 12
NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
Figure 4. TSSOP Pin Configuration
Figure 5. LFCSP Pin Configuration
Table 9. Pin Function Descriptions
Pin No. TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 LFCSP 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Mnemonic SCLK VDD DIN GND S1 D1 S2 D2 S3 D3 S4 D4 D5 S5 D6 S6 D7 S7 D8 S8 VSS SDO Description Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Most Positive Power Supply Potential. Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Ground (0 V) Reference. Source Terminal 1. This pin can be an input or an output. Drain Terminal 1. This pin can be an input or an output. Source Terminal 2. This pin can be an input or an output. Drain Terminal 2. This pin can be an input or an output. Source Terminal 3. This pin can be an input or an output. Drain Terminal 3. This pin can be an input or an output. Source Terminal 4. This pin can be an input or an output. Drain Terminal 4. This pin can be an input or an output. Drain Terminal 5. This pin can be an input or an output. Source Terminal 5. This pin can be an input or an output. Drain Terminal 6. This pin can be an input or an output. Source Terminal 6. This pin can be an input or an output. Drain Terminal 7. This pin can be an input or an output. Source Terminal 7. This pin can be an input or an output. Drain Terminal 8. This pin can be an input or an output. Source Terminal 8. This pin can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground. Serial Data Output. This pin can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. Pull this open-drain output to the supply with an external resistor. RESET/Logic Power Supply Input (VL). When this pin is low (<0.8 V), this pin acts as RESET, all switches are open, and appropriate registers are cleared to 0. Otherwise, it is the logic power supply input that operates from 2.7 V to 5.5 V.
23
20
RESET/VL
Rev. 0 | Page 11 of 20
08497-005
ADG1414
Pin No. TSSOP 24 LFCSP 21 Mnemonic SYNC Description Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following clocks. Taking SYNC high updates the switch condition. Exposed Pad. Exposed pad tied to the substrate, VSS.
N/A 1
1
EP
Exposed Pad
N/A means not applicable.
Rev. 0 | Page 12 of 20
ADG1414 TYPICAL PERFORMANCE CHARACTERISTICS
16 14 12 VDD = +12V VSS = -12V VDD = +10V VSS = -10V 18 VDD = +13.5V VSS = -13.5V 15
ON RESISTANCE ()
ON RESISTANCE ()
12
10 8 6 4 2 0 -16.5 -13.5 -10.5 -7.5 -4.5 TA = 25C IS = -10mA VDD = +15V VSS = -15V VDD = +16.5V VSS = -16.5V
TA = +125C TA = +85C TA = +25C
9
6
TA = -40C
3 VDD = +15V VSS = -15V
08497-006
-1.5
1.5
4.5
7.5
10.5 13.5 16.5
-10
-5
0 VS, VD (V)
5
10
15
VS, VD (V)
Figure 6. On Resistance as a Function of VD (VS), Dual Supply
Figure 9. On Resistance as a Function of VD (VS), for Different Temperatures, 15 V Dual Supply
30
35 30 25 20 15 10 5 0 -7 TA = 25C IS = -10mA
08497-007
VDD = +3.0V VSS = -3.0V 25 VDD = +4.5V VSS = -4.5V VDD = +5.0V VSS = -5.0V
ON RESISTANCE ()
ON RESISTANCE ()
TA = +125C 20 TA = +85C 15 TA = +25C 10 TA = -40C
VDD = +5.5V VSS = -5.5V VDD = +7V VSS = -7V
5 VDD = +5V VSS = -5V
-5
-3
-1
1
3
5
7
-4
-3
-2
-1
0 VS, VD (V)
1
2
3
4
5
VS, VD (V)
Figure 7. On Resistance as a Function of VD (Vs), Dual Supply
40 35 30 VDD = +5V VSS = 0V
Figure 10. On Resistance as a Function of VD (VS), for Different Temperatures, 5 V Dual Supply
25
20
ON RESISTANCE ()
ON RESISTANCE ()
25 20 15 10 5 0 TA = 25C IS = -10mA 0 1.5 3.0 4.5 6.0
VDD = +8V VSS = 0V VDD = +12V VSS = 0V
TA = +125C 15 TA = +85C 10 TA = +25C TA = -40C 5 VDD = +12V VSS = 0V
VDD = +10.8V VSS = 0V
VDD = +15V VSS = 0V
VDD = +13.2V VSS = 0V
08497-008
7.5
9.0
10.5
12.0 13.5
15.0
0
2
4
6 VS, VD (V)
8
10
12
VS, VD (V)
Figure 8. On Resistance as a Function of VD (VS), Single Supply
Figure 11. On Resistance as a Function of VD (VS), for Different Temperatures, 12 V Single Supply
Rev. 0 | Page 13 of 20
08497-011
0
08497-010
0 -5
08497-009
0 -15
ADG1414
2.5 VDD = +15V VSS = -15V 2.0 VBIAS = +10/-10V 1.5 1.0 0.5 0 -0.5 -1.0 -1.5
08497-013
500 VL = 5.5V ID, IS (ON) - - ID (OFF) -+ IS (OFF) +-
IDD (A)
IDD PER LOGIC INPUT TA = 25C
400
LEAKAGE CURRENT (nA)
ID, IS (ON) ++
300
200 IS (OFF) -+ 100 ID (OFF) +- VL = 2.7V 0 20 40 60 80 100 120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
08497-016
08497-018 08497-017
-2.0 TEMPERATURE (C)
0 LOGIC LEVEL (V)
Figure 12. Leakage Current as a Function of Temperature, 15 V Dual Supply
Figure 15. IDD vs. Logic Level
3.0
VDD = +5V VSS = -5V 2.5 VBIAS = +4.5/-4.5V
LEAKAGE CURRENT (nA)
80
TA = 25C
ID, IS (ON) ++
CHARGE INJECTION (pC)
60 40 20 0 -20 -40 -60 -15 VDD = +15V VSS = -15V
2.0 1.5 ID, IS (ON) - - 1.0 ID (OFF) -+ 0.5 0 -0.5 -1.0 0 20 40 60 80 100 120 TEMPERATURE (C) IS (OFF) -+ ID (OFF) +-
08497-014
VDD = +5V VSS = -5V
VDD = +12V VSS = 0V
IS (OFF) +-
-10
-5
0 VS (V)
5
10
15
Figure 13. Leakage Current as a Function of Temperature, 5 V Dual Supply
3.0
300
Figure 16. Charge Injection vs. Source Voltage
VDD = 12V VSS = 0V 2.5 VBIAS = 1V/10V
LEAKAGE CURRENT (nA)
ID, IS (ON) ++
250
2.0
200
tON (5V)
ID, IS (ON) - -
TIME (ns)
1.5 1.0 0.5 0 ID (OFF) -+ IS (OFF) +-
tON (+12V)
150
100
tON (15V) tOFF (5V)
50
-0.5 -1.0 0 20 40 60
IS (OFF) -+ 80
ID (OFF) +-
08497-015
100
120
0 -40
tOFF (15V)
-20 0 20 40 60 TEMPERATURE (C)
tOFF (+12V)
80 100 120
TEMPERATURE (C)
Figure 14. Leakage Current as a Function of Temperature, 12 V Single Supply
Figure 17. Transition Time vs. Temperature
Rev. 0 | Page 14 of 20
ADG1414
0 TA = 25C VDD = +15V VSS = -15V 0.20 LOAD = 110 0.18 TA = 25C 0.16 0.14 VDD = +5V, VSS = -5V, VS = +5V p-p
-20
OFF ISOLATION (dB)
-40
THD + N (%)
0.12 0.10 0.08 VDD = +15V, VSS = -15V, VS = +10V p-p 0.06 0.04 0.02
-60
-80
-100
08497-019
10k
100k
1M
10M
100M
1G
0
5000
10,000 FREQUENCY (Hz)
15,000
20,000
FREQUENCY (Hz)
Figure 18. Off Isolation vs. Frequency
0 -0.5 -1.0 -40 0
Figure 21. THD + N vs. Frequency, 15 V Dual Supply
TA = 25C VDD = +15V VSS = -15V
-20
TA = 25C VDD = +15V VSS = -15V
INSERTION LOSS (dB)
ACPSRR (dB)
-1.5 -2.0 -2.5 -3.0
NO DECOUPLING CAPACITORS
-60 DECOUPLING CAPACITORS
-80
-100 -3.5 -4.0 1k -120 1k
08497-012
10k
100k
1M
10M
100M
1G
10k
100k FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 19. On Response vs. Frequency
0
Figure 22. ACPSRR vs. Frequency
-20
TA = 25C VDD = +15V VSS = -15V
CROSSTALK (dB)
-40
-60
-80
-100
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 20. Crosstalk vs. Frequency
08497-021
-120 10k
Rev. 0 | Page 15 of 20
08497-025
08497-023
-120 1k
0
ADG1414 TEST CIRCUITS
IDS V1
IS (OFF) ID (OFF) S D A
08497-027
ID (ON) NC S D A
08497-028
S
D
A
08497-026
VS
RON = V1/IDS
VS
VD
NC = NO CONNECT
VD
Figure 23. On Resistance
Figure 24. Off Leakage
Figure 25. On Leakage
VDD 0.1F
VSS 0.1F NETWORK ANALYZER
0.1F
VDD
VSS 0.1F NETWORK ANALYZER
VDD S IN
VSS
VDD S
VSS
50 D
50 VS VOUT
IN D
50 VS VOUT
VIN GND
RL 50
VIN GND
08497-032
RL 50
OFF ISOLATION = 20 log
VOUT VS
INSERTION LOSS = 20 log
VOUT WITH SWITCH VOUT WITHOUT SWITCH
Figure 26. Off Isolation
Figure 28. Insertion Loss
VDD 0.1F NETWORK ANALYZER VOUT RL 50
VSS 0.1F VDD 0.1F VSS 0.1F AUDIO PRECISION VDD D R 50 S IN D GND VIN
08497-033
VDD S1
VSS VSS RS VS V p-p VOUT
08497-035
S2 VS
RL 10k GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT VS
Figure 27. Channel-to-Channel Crosstalk
Figure 29. THD + Noise
Rev. 0 | Page 16 of 20
08497-034
ADG1414
VDD 0.1F VSS 0.1F
VDD S VS
VSS D RL 300 VOUT CL 35pF SYNC 50% 50%
90% VOUT
90%
INPUT LOGIC GND
tON
tOFF
Figure 30. Switching Times
VDD VSS
3V SYNC RS VS QINJ = CL x VOUT VOUT SWITCH OFF SWITCH ON VOUT S
VDD
VSS D CL 1nF VOUT
INPUT LOGIC
08497-031
GND
Figure 31. Charge Injection
Rev. 0 | Page 17 of 20
08497-029
ADG1414 TERMINOLOGY
IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminal Dx or Terminal Sx. RON The ohmic resistance between Terminal Dx and Terminal Sx. RON The difference between the RON of any two channels. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. tON The delay between applying the digital control input and the output switching on. See Figure 30. tOFF The delay between applying the digital control input and the output switching off. See Figure 30. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) A measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.
Rev. 0 | Page 18 of 20
ADG1414 THEORY OF OPERATION
The ADG1414 is a set of serially controlled, octal SPST switches. Each of the eight bits of the 8-bit write corresponds to one switch of the device. A Logic 1 in the particular bit position turns the switch on, whereas a Logic 0 turns the switch off. Because each switch is independently controlled by an individual bit, this provides the option of having any, all, or none of the switches turned on.
POWER-ON RESET
The ADG1414 contains a power-on reset circuit. On power-up of the device, all switches are in the off condition and the internal shift register is filled with zeros and remains so until a valid write takes place. The part also has a RESET/VL pin. When the RESET/VL pin is low, all switches are off and the appropriate registers are cleared to 0.
SERIAL INTERFACE
The ADG1414 has a 3-wire serial interface (SYNC, SCLK, and DIN pins) that is compatible with SPI, QSPI, and MICROWIRE interface standards, as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. This enables the input shift register. Data from the DIN line is clocked into the 8-bit input shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the ADG1414 compatible with high speed DSPs. Data can be written to the shift register in more or less than eight bits. In each case, the shift register retains the last eight bits that were written. When all eight bits have been written into the shift register, the SYNC line is brought high again. The switches are updated with the new configuration, and the input shift register is disabled. With SYNC held high, the input shift register is disabled; therefore, further data or noise on the DIN line has no effect on the shift register. Data appears on the SDO pin on the rising edge of SCLK suitable for daisy chaining or readback, delayed by eight bits.
DAISY CHAINING
For systems that contain several switches, the SDO pin can be used to daisy-chain several devices together. The SDO pin can also be used for diagnostic purposes and provide serial readback, wherein the user can read back the switch contents. SDO is an open-drain output that should be pulled to the VL supply with an external resistor. The SCLK is continuously applied to the input shift register when SYNC is low. If more than eight clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting this line to the DIN input on the next device in the chain, a multiswitch interface is constructed. Each device in the system requires eight clock pulses; therefore, the total number of clock cycles must equal 8N, where N is the total number of devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This prevents any further data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock. A continuous SCLK source can be used only if SYNC can be held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. Gated clock mode reduces power consumption by reducing the active clock time.
INPUT SHIFT REGISTER
The input shift register is eight bits wide (see Table 10). Each bit controls one switch. These data bits are transferred to the switch register on the rising edge of SYNC. Table 10. ADG1414 Input Shift Register Bit Map1
MSB DB7 S8
1
LSB DB6 S7 DB5 S6 DB4 S5 DB3 S4 DB2 S3 DB1 S2 DB0 S1
Logic 0 = switch off and Logic 1 = switch on.
Rev. 0 | Page 19 of 20
ADG1414 OUTLINE DIMENSIONS
7.90 7.80 7.70
24
13
4.50 4.40 4.30 6.40 BSC
1 12
PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD 1.20 MAX
SEATING PLANE
0.20 0.09
8 0
0.75 0.60 0.45
Figure 32. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters
4.00 BSC SQ
0.60 MAX 0.60 MAX
19 18 EXPOSED PAD
(BO TTOMVIEW)
PIN 1 INDICATOR
24 1
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
2.65 2.50 SQ 2.35
6
13 12
7
0.23 MIN
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
2.50 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8
Figure 33. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG1414BRUZ 1 ADG1414BRUZ-REEL71 ADG1414BCPZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C
Package Description 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
082908-A
SEATING PLANE
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Package Option RU-24 RU-24 CP-24-3
Z = RoHS Compliant Part.
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08497-0-10/09(0)
Rev. 0 | Page 20 of 20

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